The present invention relates to a memory device coupled to a processor of a data flow (driven) type, and more particularly to a memory device inserted in a token ring bus through which a data stream is transferred according to data flow architecture.
Hitherto, memory access from a processor of a data flow type is effected as follows.
The data flow type processor transfers information called a "token", including an address, a data to be manipulated and at least one instruction code indicating an operation such as a read operation and a write operation for the memory device, at a timing through a bus. The memory device may include a memory chip or chips formed on a printed board and a control chip also formed thereon. The memory device has external input terminals (pins) for simultaneously receiving the address, data and instruction code from the bus and a decoder for decoding the instruction code in the received token.
According to the decoding, if the instruction code indicates a read operation, the address in the received token is used as a read out address to read a data previously stored in the memory device. The read out data is derived from external output terminals to outside of the memory device. In this operation, a data in the received token is ignored. While if the instruction code indicates a write operation, the address in the received token is used as a write address by which the data in the received token is written into the memory device.
It will be noted that the above-mentioned memory device used in the data flow processing system is different from a well known normal memory device in that a data, an address and an instruction code are applied simultaneously or at the same timing to the memory device and that an instruction decoder is provided in the memory device. Specifically, both a memory section and a decoder section may be formed on a single semiconductor memory chip or on a printed board.
In such a data flow processing system, the memory access operation can be performed at a high speed since an instruction, an address and a data are applied simultaneously or at the same timing to the memory device, but an extremely great number of bus lines between the processor and the memory device are required. This is problematic particularly when a processor is fabricated using a single chip LSI (large scale semiconductor integration) circuit in which the number of pins is limited to a small value. In other words, the bit length of the token supplied from the processor to the memory device is too small (for example, 16 bits) to be assigned to all the needed information, including the data to be written into the memory device, the address of the memory device, etc. Namely, this system faces drawbacks that if a large number of pins are required, an LSI package becomes costly as the size of the package increases and an occupied area of the package and bus lines on a printed board becomes large. The memory device per se suffers from similar shortcomings.
Further, from a viewpoint of the trend toward multiprocessor systems being recently developed, it is required that a commonly used memory device be smoothly accessed from a plurality of processors at an arbitrary timing.